1. Field of the Invention
This invention relates generally to sample and hold circuits and particularly to a sample and hold circuit of a diode bridge type.
2. Description of the Prior Art
FIGS. 1 and 2 respectively show examples of a conventional sample and hold circuit. According to the conventional sample and hold circuit of FIG. 1, a pulse is supplied through a transformer in which series circuits of diodes D1, D2 and D3, D4 in a diode bridge circuit 1 are connected in parallel between one end and the other end of the secondary coil of the transformer. A connection point between a cathode of the diode D1 and an anode of the diode D2 is led out as an input terminal 10, while a connection point between a cathode of the diode D3 and an anode of the diode D4 is led out as an output terminal 11. Between the output terminal 11 and the ground is connected a capacitor 12 for holding. Accordingly, when the connection point between the anodes of the diodes D1 and D3 becomes at higher level than the connection point between the cathodes of the diodes D2 and D4, the diodes D1 to D4 in the diode bridge 1 are all made ON to connect the input terminal 10 with the output terminal 11 so that the output voltage equals to the input voltage. While, if the above relation of level is reversed, the diodes D1 to D4 are all made OFF to cut off between the input terminal 10 and the output terminal 11 so that charges stored in the capacitor 12 are held.
The circuitry shown in FIG. 1 employs the transformer and is therefore unsuitable for it to be formed as an integrated circuit (IC). For this reason, as shown in FIG. 2, there is proposed the sample and hold circuit in which the diode bridge 1 is driven by transistors 2 and 3 that are arranged as a differential amplifier. In this circuitry, a constant current source 4 for supplying a constant current I.sub.1 is connected between a connection point of the emitters of the transistors 2 and 3 and the ground and switching pulses opposite in phase are respectively supplied to terminals 5 and 6 led out from the bases thereof whereby the transistors 2 and 3 differentially carry out switching operations. Resistors 7 and 8 are connected between each collector of the transistors 2 and 3 and a power source terminal 9 for a source voltage +Vcc.
With the afore-said circuitry shown in FIG. 2, if a potential at the terminal 5 is made higher than that at the terminal 6, the transistor 2 is made ON and the transistor 3 is made OFF so that current flowing through the resistors 7 and 8 and the diode bridge 1 flows through the transistor 2. Thus, all the diodes D1 to D4 in the diode bridge 1 are made ON and hence a voltage Vo at the output terminal 11 equals to an input voltage Vi at the input terminal 10.
Next, if the voltage at the terminal 5 is made lower than that at the terminal 6, all the diodes D1 to D4 in the diode bridge 1 are made OFF so that the output terminal 11 is cut off from the collectors of the transistors 2 and 3 thus the charges stored in the capacitor 12 are held.
By the way, it is noted that this circuitry has such a problem that stray capacities Cd including a junction capacity exist in parallel to the diodes D1 to D4 and this causes a pulse voltage to be leaked to the input and output terminals as an error voltage component.
This problem will be described below. When the diode bridge 1 is made ON, a collector voltage Va of the transistor 2 becomes Vo-Vf (where Vf represents the forward voltage of the diodes D1 to D4), while a collector voltage Vb of the transistor 3 becomes Vo+Vf. Next, when the diode bridge 1 is made OFF, the collector voltage Va of the transistor 2 is increased up to the source voltage Vcc, while the collector voltage Vb of the transistor 3 is lowered to Vm (=Vcc-I.sub.1 R8)(where R8 represents the resistance value of the resistor R8) so that an amplitude of the collector voltage Va of the transistor 2 which changes in association with ON and OFF of the diode bridge 1 becomes [Vcc-(Vo-Vf)], while an amplitude of the collector voltage Vb of the transistor 3 becomes [(Vo+Vf)-Vm]. The change of the amplitudes affects the output voltage Vo by way of the stray capacity Cd. If the capacitance value of the capacitor 12 for holding is taken as C, this error voltage component is given as: ##EQU1## As is clear from this equation, the error voltage component varys with the magnitude of the output voltage Vo so that linearity becomes poor and hence this error voltage component can not be removed. Therefore, the component of the pulse voltage to be applied to the terminals 5 and 6 appears at the output terminal 11 so that precision of the output voltage Vo is lowered. Furthermore, unlike the circuitry using the transformer shown in FIG. 1, the circuit arrangement in FIG. 2 is required to flow the constant current I.sub.1 at all times, leading to a large power consumption.